structure and function of the processor

• completes all arithmetic and logic functions

• results are often stored in general-purpose registers (e.g. the ACC)

• arithmetic operations on fixed/floating point numbers (e.g. ADD, SUBTRACT, MULTIPLY or DIVIDE)

• bitwise shift operations

• boolean logic operations (e.g. comparisons, AND, OR, NOT or XOR)

• coordinates all activities of the CPU

• accepts and decodes instructions

• sends memory read/write requests to RAM along the control bus

• sends control signals

  • e.g bus requests/grants, or interrupt requests

• makes extensive use of the status registers and clock

• communicates with all elements of the CPU

registers are small memory cells that operate at a very high speed, they are used to temporarily store data

• holds the address of the next instruction to be executed

• this could be:

  • the next instruction in a sequence

  • an address to jump to, if the previous instruction was to branch (copied from the CIR)

• at the start of every FDE cycle, the instruction in the PC is copied to the MAR

• used to temporarily store data/instructions that are to be written to memory, or have been read from memory

• contents of MDR are copied to the CIR (if MDR contains an instruction)

• acts as a buffer

• holds the address of a memory location from which data or an instruction is to be fetched, or which data is to be written to

• sends this address to memory down the address bus

• it is either the address of an instruction (to be accessed in memory) sent from PC…

• or the address of data (to be accessed in memory) sent from CIR

• data and control information often stored here

• stores the results of operations performed in the ALU

• temporary storage for data being processed during calculations

• I/O in processor, used as a buffer

• holds the current instruction being executed

• contents of MDR are copied to the CIR (if MDR contains an instruction)

• contains the opcode and operand(s) of the instruction

buses are a set of parallel wires which connect two or more components inside the CPU

• the width of the bus is the number of parallel wires the bus has:

  • the width of the bus is directly proportional to the number of bits that can be transferred simultaneously at any given time

  • buses are typically 8, 16, 32 or 64 wires wide

a bi-directional bus that transports data and instructions (in binary) between components

transmits memory addresses specifying where data or instructions are to be sent to/retrieved from

• transmits control signals between internal/external components

• coordinates the use of the address and data buses

• provides status information between system components

a control signal that shows that a device is requesting the use of the data bus

a control signal that shows that the CPU has granted access to the data bus

a control signal that requests that data is written into the addressed location using the data bus

a control signal that requests that data is read from a specific location to be placed onto the data bus

a control signal that shows that a device is requesting access to the CPU

the cycle that a CPU follows to process and execute a instruction

• address of the next instruction is copied from PC to MAR

• contents of MAR are sent along the address bus to memory, where it waits to receive a signal from the control bus

• the data/instruction held in the corresponding memory address is copied to MDR by the data bus

• if MDR holds an instruction, its contents are copied to CIR

• PC is incremented by 1

• the instruction in CIR is split into opcode and operand

• the instruction is decoded in the decode unit

• the instruction is executed, for example…

  • performing arithmetic operations in the ALU

  • storing the contents of the accumulator in a memory address in RAM

• clock speed is the number of clock cycles completed per second

• clock speed is determined by the system clock (an electronic device which generates signals, switching periodically between 0 and 1)

all processor activities begin on a clock pulse, and each CPU operation starts as the clock changes from 0 to 1

• measured in GigaHertz (GHz)

• one GHz is one billion instructions fetched per second

an independent processor that is able to run its own FDE cycle

computers with multiple cores can complete multiple FDE cycles at once

• a computer with dual cores can theoretically complete tasks twice as fast as a computer with a single core, however..

  • not all programs are able to utilise multiple cores efficiently as they have not been designed to do so

  • inter-core communication also requires processor time

• cache memory is located on or near the CPU

• much faster to access than RAM

• instructions fetched from main memory are copied to the cache, so if required again, they can be accessed quicker

• as cache fills up, unused instructions are replaced

• pipelining is the process of completing the FDE cycles of separate instructions simultaneously and holding appropriate data in a buffer in close proximity to the CPU until it’s required

• it aims to reduce the amount of the CPU which is kept idle

• it is separated into instruction pipelining and arithmetic pipelining

separating out the instruction into fetching, decoding, and executing

breaking down the arithmetic operations and overlapping them as they are performed

• pipelining is inefficient when programs contain lots of branching

• as each time a program branches the processor will have to ‘flush the pipe’

• instructions and data stored in separate memory units

• each has its own bus

• reading and writing data can be done at the same time as fetching an instruction

• used in RISC processors

• shared memory space for data and instructions

• built on the ‘stored program’ concept

• instructions and data stored in the same format

• a single control unit follows a linear FDE cycle

• one instruction at a time

• cheaper to develop, control unit is easier to design

• programs can be optimised in size

• quicker execution as data and instructions can be fetched in parallel

• memories can be different sizes, makes efficient use of space