INTEL I/O Interface

One type of instruction transfers information to an I/O device.

One type of instruction reads from an I/O device.

found except the 8086/8088, instructions are also provided to transfer strings of data between memory and I/O.

Instructions that transfer data between an I/O device and the microprocessor’s accumulator (AL, AX, or EAX).

The I/O address is stored in register __ as a 16 bit address or in the byte (p8) immediately following the opcode as an 8 bit address.

Intel calls the 8 bit form (p8) a ___because it is stored with the instruction, usually in a ROM.

The 16 bit address is called a ____ because it is stored in a DX, and then used to address the I/O device.

I/O ports are ___ in width.

a 16 bit port is actually ___consecutive 8 bit ports being addressed.

a 32 bit I/O port is actually __ 8 bit ports.

When data are transferred using IN or OUT, the I/O address ___ appears on the address bus.

decodes the port number in the same manner as a memory address.

8 bit fixed port number appears on address bus connections Asub7 to Asub0 with bits Asub15 to Asub8 equal to 00000000sub2.

connections above __ are undefined for I/O instruction.

The 16 bit variable port number appears on address connections A 15 A 0.

The first __ I/O port addresses (00H FFH) are accessed by both fixed and variable I/O instructions.

any I/O address from 0100H to FFFFH is only accessed by the ___.

Two different methods of interfacing I/O.

the IN, INS, OUT, and OUTS transfer data between the microprocessor’s accumulator or memory and the I/O device. Most common I/O transfer technique used in the Intel based system is isolated I/O.

describes how I/O locations are isolated from memory in a separate I/O address space.

any instruction that references memory can accomplish the transfer.

are used to control peripheral devices.

address is used to access devices located on the system board, such as the timer and keyboard interface.

is used to access serial and parallel ports, video and disk drive Systems.

does not use the IN, INS, OUT, or OUTS instructions. It uses any instruction that transfers data between the microprocessor and memory.

I/O space between ports 0000H and 03FFH is normally reserved for the system and __.

ports at 0400H FFFFH are generally available for user applications, main board functions, and the PCI bus.

uses 00F8H 00FFH, so Intel reserves I/O ports 00F0H 00FFH.

The basic input device is a set of three state ___ and three state ___ are used to construct the 8 bit input port.

The basic output device is a set of data ___.

The term __ refers to moving data from the I/O device into the microprocessor.

The term ___ refers to moving data out of the microprocessor to the I/O device.

The circuit of allows the processor to read the contents of the eight switches that connect to any 8 bit section of the data bus when the select signal becomes a ___.

is a three state buffer that controls the application of the switch data to the data bus.

hold the data because when the processor executes an OUT, data are only present on the data bus for less than 1.0 µ s.

synchronizes the I/O device with the microprocessor or the process of interrogating the printer, or any asynchronous device like a printer.

is a clock pulse used to send data to printer.

are already TTL and compatible, and can be connected to the microprocessor and its interfacing components.

ensures when the switch is open, the output signal is a logic 1.

are more diverse than input devices, but many are interfaced in a uniform manner.

the diode must be present to prevent the ___ from being destroyed by inductive kickback.

is a better decoder circuit because the number of integrated circuits has been reduced to one device.

The Darlington pair must use a ___ because of the amount of current.

Very similar to memory address decoding especially for memory mapped I/O devices.

In the ___, we always decode all 16 bits of the I/O port address, never uses or decodes an 8 bit address.

(a low-cost device) for decoder

Data transferred to an 8 bit I/O device exist in one of the I/O banks in a 16 bit processor such as ____.

Data transferred to an 8 bit I/O device exist in one of the I/O banks in a 16 bit processor such as 80386SX.

May eventually become common because of newer buses found in computer systems.

is a popular, low cost interface component found in many applications.

The PPI has __ pins for I/O, programmable in groups of 12 pins and groups that operate in three distinct modes of operation.

is used for interface to the keyboard and parallel printer port in many PCs.

C0H (port A), C2H (port B), C4H (port C), and C6H (command register).

A ____ to 82C55 sets up all ports as simple input ports using mode 0 operation.

causes 82C55 to function as a buffered input device or as a latched output device.

have replaced LED displays in many applications.

is a 4 line by 20 characters per line display that accepts ASCII code as input data.

procedure tests the LCD display and only returns when the display has completed a prior instruction.

Once the BUSY procedure is available, data can be sent to the display by writing another procedure called ___.

The only other procedure needed for a basic display is the clear & home cursor procedure, called ___.

a digital motor because it is moved in discrete steps as it traverses through 360*.

The motor is shown with the armature rotated to four discrete places, called ___.

the switches are formed into a 4X4 matrix, but any matrix could be used, such as a 2X8.

Causes port A and/or port B to function as latching input devices which allows external data to be stored to the port until the microprocessor is ready to retrieve it.

The ___ input loads data to the port latch, which holds the information until it is input to the microprocessor via the IN instruction.

is an output indicating that the input latch contains information.

is an output that requests an interrupt.

The port C pins _ and _ are general purpose I/O pins that are available for any purpose.

Strobed output operation is similar to mode 0 except control signals are included to provide handshaking.

goes low whenever data are output (OUT) to the port A or B latch, is an output indicating the output buffer contains data.

causes the OBF pin to return to logic 1 and is a response from an external device, indicating that it has received data from the 82C55 port.

often interrupts the processor when the external device receives the data via the ACK signal.

is neither input nor output; it is an internal bit programmed to enable or disable the INTR pin.

Port C pins _ and _ are general purpose I/O pins.

Port A becomes bidirectional, allowing data transmit/receive over the same eight wires, useful when interfacing two computers.

is an input that enables the three state buffers so that data can appear on port A.

input loads the port A input latch with external data from the bidirectional port A bus.

These pins are general purpose I/O pins in mode 2 controlled by the bit set and reset command.\

is an output used to signal that the input buffer contains data for the external bidirectional bus.

is used by referencing port A with the IN and OUT instructions.

consists of three independent 16 bit programmable counters ( timers ).

The address inputs select one of four internal registers within the 8254.

input is the timing source for each of the internal counters.

enables 8254 for programming and reading or writing a counter.

controls the operation of the counter in some modes of operation.

connects to the system ground bus.

is where the waveform generated by the timer is available.

causes data to be read from the 8254 and often connects to the IORC signal.

connects to the +5.0 V power supply.

causes data to be written to the 8254 and often connects to write strobe IOWC.

Allows 8254 to be used as an events counter.

Causes function as a retriggerable, monostable multivibrator (one shot).

Allows the counter to generate a series of continuous pulses one clock pulse wide.

Generates a continuous square wave at the OUT connection, provided the G pin is logic 1.

Allows a single pulse at the output.

A hardware triggered one shot that functions as mode 4.

Each counter generates pulses at different positions to vary the duty cycle at the Q output of the flip flop and this output is also called.

is a programmable communications interface designed to connect to virtually any type of serial interface.